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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7404 5-Bit x 64-word FIFO register; 3-state
Product specification Supersedes data of October 1990 File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
FEATURES * Synchronous or asynchronous operation * 3-state outputs * 30 MHz (typical) shift-in and shift-out rates * Readily expandable in word and bit dimensions * Pinning arranged for easy board layout: input pins directly opposite output pins * Output capability: driver (8 mA) * ICC category: LSI. APPLICATIONS * High-speed disc or tape controller * Communications buffer. GENERAL DESCRIPTION
74HC/HCT7404
The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The "7404" is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. TYP. SYMBOL tPHL/tPLH fmax CI CPD Note 1. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC -1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7404N 74HC/HCT7404D PACKAGE PINS 18 20 PIN POSITION DIL SO20 MATERIAL plastic plastic CODE SOT102 SOT163A PARAMETER propagation delay SO, SI to DIR and DOR maximum clock frequency input capacitance power dissipation capacitance per package note 1 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 30 3.5 475 HCT 17 30 3.5 490 ns MHz pF pF UNIT
September 1993
2
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
PINNING (SOT102) SYMBOL OE DIR SI DO to D4 GND MR Q4 to Q0 DOR SO VCC PIN 1 2 3 9 10 11, 12, 13, 14, 15 16 17 18 DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) ground asynchronous master-reset input (active LOW) data outputs Q4 to Q0 data-out-ready output shift-out input (active LOW) positive supply voltage n.c. DOR n.c. VCC 12, 13, 14, 15, 16 17 18 19 20 PINNING (SOT163A) SYMBOL OE DIR SI n.c. D0 to D4 GND MR PIN 1 2 3 4 10 11
74HC/HCT7404
DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) not connected ground asynchronous master-reset input (active LOW) data outputs not connected data-out ready output not connected positive supply voltage
4, 5, 6, 7, 8 parallel data inputs
5, 6, 7, 8, 9 parallel data inputs
handbook, halfpage handbook, halfpage
OE OE DIR SI D0 D1 D2 D3 D4 GND 1 2 3 4 5 6 7 8 9
MGA670
1 2 3 4 5
18 V CC 17 SO
20 V CC 19 SO 18 DOR 17 n.c. 16 Q0
DIR SI
16 DOR n.c. 15 Q0 D0 D1 D2 D3 D4
7404
14 Q1 13 Q2 12 Q3 11 Q4 10 MR
7404
6 7 8 9 15 Q1 14 Q2 13 Q3 12 Q4 11 MR
MGA671
GND 10
Fig.1 Pin configuration (SOT102).
Fig.2 Pin configuration (SOT163).
September 1993
3
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, halfpage
1 (1)
handbook, halfpage
FIFO 64 x 5 EN4 1Z3 [IR] 3 [OR] 6 G1 G5 2 (2) 16 (18)
(1) 1 OE (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 D0 D1 D2 D3 D4 SI SO MR 10 (11)
MGA673
Q0 Q1 Q2 Q3 Q4 DOR DIR
15 (16) 14 (15) 13 (14) 12 (13) 11 (12) (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 (3) 3 (11) 10 (19) 17
CTR 1 ( /C2) CT < 64 CT = 0 CT > 0 5 5Z6 2D
(3) 3 (19) 17
16 (18) 2 (2)
4
15 (16) 14 (15) 13 (14) 12 (13) 11 (12)
MGA675
Pin numbers between parentheses refer to the SO package.
Pin numbers between parentheses refer to the SO package.
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
handbook, full pagewidth
(5) 4 D0 (6) 5 D1 (7) 6 D2 (8) 7 D3 (9) 8 D4 INPUT STAGE 1 x 5 BITS MAIN FIFO REGISTER 62 x 5 BITS OUTPUT STAGE 1 x 5 BITS
Q 0 15 (16) Q 1 14 (15) Q 2 13 (14) Q 3 12 (13) OE Q 4 11 (12)
(11) 10 MR DIR 2 (2) SI
CONTROL LOGIC DOR SO OE 1 (1)
MGA680
3 (3)
16 (18) 17 (19)
Pin numbers between parentheses refer to the SO package.
Fig.5 Functional diagram.
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4
full pagewidth
R (1) R S Q FP DOR
September 1993
SO
Philips Semiconductors
MR
61 x
SI
(1) R R FF1 S Q S Q S R FF2 R FF64 Q Q R Q R R Q
(2)
(2)
(2)
(1)
R
FS
5-Bit x 64-word FIFO register; 3-state
S
Q
Q FF3 R to FF63 S Q
R S
FB Q
5
OE CL CL CL CL CL CL CL Q0 Q1 5 LATCHES 5 LATCHES 5 LATCHES 3-STATE OUTPUT BUFFER Q3 Q4 position 2 position 3 to 63 position 64
MSB117
DIR
D0
CL
D1
5 LATCHES
D3
D4
position 1
(See control flip-flops) LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input. LOW on R input of FF1 to FF64 will set Q output to LOW independent of state on S input.
74HC/HCT7404
Product specification
Fig.6 Logic diagram.
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
FUNCTIONAL DESCRIPTION The DIR flag indicates the input stage status, either empty and ready to receive data (DIR = HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to D4 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW, data is automatically shifted to the output stage or to the last empty location. A FIFO which can receive data is indicated by DIR set HIGH. A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy (DOR = LOW). When SO and DOR are HIGH, data is available at the DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI Output capability: driver 8 mA ICC category: LSI Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HC Tamb C SYMBOL PARAMETER MIN VOH HIGH level output voltage LOW level output voltage 3.98 5.48 - - +25 TYP 4.32 5.81 0.15 0.15 MAX - - 0.26 0.26 -40 to +85 MIN 3.84 5.34 - - - - 0.33 0.33 outputs (Q0 to Q4). When SO is LOW new data may be shifted into the output stage, once complete DOR is set LOW. Expanded Format (see Fig.18) The DOR and DIR signals are used to allow the `7404' to be cascaded. Both parallel and serial expansion is possible. Serial expansion is only possible with typical devices. Parallel Expansion Parallel expansion is accomplished by logically ANDing the DOR and DIR signals to form a composite signal.
74HC/HCT7404
Serial Expansion Serial expansion is accomplished by: * tying the data outputs of the first device to the data inputs of the second device * connecting the DOR pin of the first device to the SI pin of the second device * connecting the SO pin of the first device to the DIR pin of the second device.
TEST CONDITION -40 to +125 UNIT V CC (V) MAX MIN MAX 3.70 5.20 - - - - 0.4 0.4 V V V V 4.5 6 4.5 6 VI VIH or VIL VIH or VIL OTHER IO = -8 mA IO = -10 mA IO = 8 mA IO = 10 mA
VOL
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb C SYMBOL PARAMETER MIN tPHL/tPLH propagation delay MR to DIR, DOR propagation delay MR to Qn propagation delay SI to DIR propagation delay SO to DOR propagation delay DOR to Qn propagation delay SO to Qn propagation delay/ripple through delay SI to DOR - - - - - - - - - - - - - - - - - - - - - +25 TYP 69 25 20 52 19 15 66 24 19 94 34 27 11 4 3 105 38 30 2.2 0.8 0.6 2.8 1.0 0.8 44 16 13 50 18 14 14 5 4 11 4 3 22 8 6 MAX 210 42 36 160 32 27 205 41 35 290 58 49 35 7 6.0 325 65 55 7.0 1.4 1.2 9.0 1.8 1.5 150 30 26 150 30 26 60 12 10 - - - - - - -40 to +85 MIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 9 8 90 18 15 MAX 265 53 45 200 40 34 255 51 43 365 73 62 45 9 8 406 81 69 8.8 1.8 1.5 11.2 2.2 1.9 190 38 32 190 38 33 75 15 13 - - - - - - 7 -40 to +125 MIN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55 11 9 105 21 18 MAX 315 63 54 240 48 41 310 62 53 435 87 74 55 11 9 488 98 83 10.5 2.1 1.8 13.5 2.7 2.3 225 45 38 225 45 38 90 18 15 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
74HC/HCT7404
TEST CONDITION VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.9
tPHL
Fig.9
tPHL/tPLH
Fig.7
tPHL/tPLH
Fig.10
tPHL/tPLH
Fig.11
tPHL/tPLH
Fig.15
tPLH
Fig.16
tPLH
- propagation delay/bubble-up - - delay SO to DIR 3-state output enable OE to Qn 3-state output disable OE to Qn - - - - - -
Fig.8
tPZH/tPZL
Fig.17
tPHZ/tPLZ
Fig.17
tTHL/tTLH
output transition - time - - SI pulse width HIGH or LOW SO pulse width HIGH or LOW 35 7 6 70 14 12
Fig.17
tW
Fig.7
tW
Fig.10
September 1993
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
Tamb C SYMBOL PARAMETER MIN tW DIR pulse width 10 HIGH 5 4 DOR pulse width HIGH MR pulse width LOW removal time MR to SI set-up time Dn to SI hold time Dn to SI 14 7 6 120 24 20 80 16 14 -8 -4 -3 135 27 23 +25 TYP 41 15 12 52 19 15 39 14 11 24 8 7 -36 -13 -10 44 16 13 9.9 30 36 9.9 30 36 7.6 23 27 MAX 130 26 22 160 32 27 - - - - - - - - - - - - - - - - - - - - - -40 to +85 MIN 8 4 3 12 6 5 150 30 26 100 20 17 -6 -3 -3 170 34 29 2.8 14 16 2.8 14 16 - - - MAX 165 33 28 200 40 34 - - - - - - - - - - - - - - - - - - - - - -40 to +125 MIN 8 4 3 12 6 5 180 36 31 120 24 20 -6 -3 -3 205 41 35 2.4 12 14 2.4 12 14 - - - MAX 195 39 33 240 48 41 - - - - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz MHz MHz MHz MHz UNIT
74HC/HCT7404
TEST CONDITION VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.8
tW
Fig.11
tW
Fig.9
trem
Fig.16
tsu
Fig.14
th
Fig.14
fmax
maximum clock 3.6 pulse frequency 18 SI, SO burst 21 mode maximum clock 3.6 pulse frequency 18 21 SI, SO using flags maximum clock - pulse frequency - SI, SO - cascaded
Fig.12 and Fig.13
fmax
Fig.7 and Fig.10
fmax
Fig.7 and Fig.10
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
DC CHARACTERISTICS FOR 74HCT
74HC/HCT7404
For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications", except that VOH and VOL are not valid for driver output. They are replaced by the values given below. Output capability: driver 8 mA ICC category: LSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HCT Tamb C SYMBOL PARAMETER MIN VOH HIGH level output voltage LOW level output voltage 3.98 +25 TYP 4.32 MAX - -40 to +85 MIN 3.84 - -40 to +125 UNIT V CC (V) MAX MIN MAX 3.7 - V 4.5 TEST CONDITION VI VIH or VIL VIH or VIL OTHER IO = -8 mA
VOL
-
0.15
0.26
-
0.33
-
0.40
V
4.5
IO = 8 mA
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT INPUT OE SI Dn MR SO UNIT LOAD COEFFICIENT 1 1.5 0.75 1.5 1.5
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb C SYMBOL PARAMETER MIN tPHL/tPLH propagation delay MR to DIR, DOR propagation delay MR to Qn propagation delay SI to DIR propagation delay SO to DOR propagation delay SO to Qn propagation delay DOR to Qn propagation delay/ripple through delay SI to DOR propagation delay/bubbleup delay SO to DIR 3-state output enable OE to Qn 3-state output disable OE to Qn output transition time SI pulse width HIGH or LOW SO pulse width HIGH or LOW - +25 TYP 30 MAX 51 -40 to +85 MIN - MAX 53 -40 to +125 MIN - MAX 63 ns UNIT
74HC/HCT7404
TEST CONDITION VCC (V) 4.5 WAVEFORMS Fig.9
tPHL
-
22
38
-
48
-
57
ns
4.5
Fig.9
tPHL/tPLH
-
25
43
-
54
-
65
ns
4.5
Fig.7
tPHL/tPLH
-
36
61
-
76
-
92
ns
4.5
Fig.10
tPHL/tPLH
-
42
72
-
90
-
108
ns
4.5
Fig.15
tPHL/tPLH
-
7
12
-
15
-
18
ns
4.5
Fig.11
tPLH
-
0.8
1.4
-
1.75
-
2.1
s
4.5
Fig.11
tPLH
-
1
1.8
-
2.25
-
2.7
s
4.5
Fig.8
tPZH/tPZL
-
16
30
-
38
-
45
ns
4.5
Fig.17
tPHZ/tPLZ
-
19
30
-
38
-
45
ns
4.5
Fig.17
tTHL/tTLH tW tW tW
- 9 14
5 5 8 17
12 - - 29
- 6 18 4
15 - - 36
- 8 21 4
18 - - 44
ns ns ns ns
4.5 4.5 4.5 4.5
Fig.17 Fig.7 Fig.10 Fig.8
DIR pulse width 5 HIGH
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
Tamb C SYMBOL PARAMETER MIN tW tW trem tsu th fmax DOR pulse width HIGH MR pulse width LOW removal time MR to SI set-up time Dn to SI hold time Dn to SI maximum clock pulse frequency SI, SO burst mode maximum clock pulse frequency SI, SO using flags maximum clock pulse frequency SI, SO cascaded 7 26 18 -5 30 18 +25 TYP 21 15 10 -16 18 30 MAX 36 - - - - - -40 to +85 MIN 6 33 23 -4 38 14 MAX 45 - - - - - -40 to +125 MIN 6 39 27 -4 45 12 MAX 54 - - - - - ns ns ns ns ns MHz UNIT
74HC/HCT7404
TEST CONDITION VCC (V) 4.5 4.5 4.5 4.5 45 4.5 WAVEFORMS Fig.11 Fig.9 Fig.16 Fig.14 Fig.14 Fig.12 and Fig.13
fmax
18
30
-
14
-
12
-
MHz
4.5
Fig.7 and Fig.10
fmax
-
23
-
-
-
-
-
MHz
4.5
Fig.7 and Fig.10
September 1993
11
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
AC WAVEFORMS Shifting in sequence FIFO empty to FIFO full
74HC/HCT7404
handbook, full pagewidth
1st word 1/f max
2nd word
64th word
SI INPUT
2
VM (1) 4 tW
VM (1) 6
t PHL 1 DIR OUTPUT 3
t PLH 5 7
Dn INPUT
MGA659
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum pulse frequency.
Notes to Fig.7 1. DIR initially HIGH; FIFO is prepared for valid data 2. SI set HIGH; data loaded into input stage 3. DIR goes LOW, input stage "busy" 4. SI set LOW; data from first location "ripple through" 5. DIR goes HIGH, status flag indicates FIFO prepared for additional data 6. Repeat process to load 2nd word through to 64th word into FIFO DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
September 1993
12
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
With FIFO full; SI held HIGH in anticipation of empty location
74HC/HCT7404
handbook, full pagewidth
SO INPUT
2
VM
(1)
SI INPUT
1
VM (1) t PLH bubble - up delay tW 5
DIR OUTPUT 3
VM (1) 4
MGA660
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
Notes to Fig.8 1. FIFO is initially full, shift-in is held HIGH 2. SO pulse; data in the output stage is unloaded, "bubble-up" process of empty location begins 3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input 4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again 5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
September 1993
13
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
Master reset applied with FIFO full
74HC/HCT7404
handbook, halfpage
MR INPUT
2
VM (1) tW t PLH
DIR OUTPUT
VM (1) 3 1 t PHL 4
DOR OUTPUT
VM (1) t PHL
Qn OUTPUT
5
MGA668
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width.
Notes to Fig.9 1. DIR LOW, output ready HIGH; assume FIFO is full 2. MR pulse LOW; clears FIFO 3. DIR goes HIGH; flag indicates input prepared for valid data 4. DOR goes LOW; flag indicates FIFO empty 5. Qn outputs go LOW (only last bit will be reset).
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
1st SO pulse 1/f max VM (1) 4 tW t PHL 1 DOR OUTPUT 3 t PLH 5 VM (1)
2nd SO pulse
64th SO pulse
SO INPUT
2
VM (1) 6
7
Qn OUTPUT
1st word
2nd word
64th word
MGA661
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the SO input to DOR output propagation delay, the SO pulse widths and maximum pulse frequency.
Notes to Fig.10 1. DOR HIGH; no data transfer in progress, valid data is present at output stage 2. SO set HIGH; results in DOR going LOW 3. DOR goes LOW; output stage "busy" 4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location "bubbles-up" to input stage 5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay 6. Repeat process to unload the 3rd through to the 64th word from FIFO. 7. DOR remains LOW; FIFO is empty.
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
With FIFO empty; SO is held HIGH in anticipation
74HC/HCT7404
handbook, full pagewidth
SI INPUT
2
VM
(1)
SO INPUT
1
VM (1) t PLH ripple through delay tW
6
DOR OUTPUT
3
VM
(1)
5 t PHL t PLH
Qn OUTPUT
4
MGA669
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation delay from the DOR pulse to the Qn output.
Notes to Fig.11 1. FIFO is initially empty, SO is held HIGH 2. SI pulse; loads data into FIFO and initiates ripple through process 3. DOR flag signals the arrival of valid data at the output stage 4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the DOR pulse to the Qn output 5. DOR goes LOW; data shift-out is complete, FIFO is empty again 6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
Shift-in operation; high-speed burst mode
74HC/HCT7404
handbook, full pagewidth
1/ f max tW
SI INPUT
VM (1)
Dn INPUT
DIR OUTPUT
MGA662
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst mode.
Note to Fig.12 In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored.
September 1993
17
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
Shift-out operation; high-speed burst mode
74HC/HCT7404
handbook, full pagewidth
1/ f max tW
SO INPUT
VM (1)
Qn OUTPUT
DOR OUTPUT
MGA663
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out burst mode.
Note to Fig.13 In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The DOR flag is a don't care condition and an SO pulse can be applied without regard to the flag.
September 1993
18
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
Dn INPUT
VM (1) t su th t su th
SI INPUT
VM (1)
MGA657
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.14 Waveforms showing hold and set-up times for Dn input to SI input.
handbook, full pagewidth
SO INPUT
VM (1)
t PLH
t PHL
Qn OUTPUT t TLH
VM (1) t THL
MGA664
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveforms showing SO input to Qn output propagation delays and output transition time.
handbook, halfpage
MR INPUT
VM (1)
t rem
SI INPUT (1) HC : HCT : VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
VM (1)
MGA665
Fig.16 Waveform showing the MR input to SI input removal time.
September 1993
19
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
tr 90 % OE INPUT 10 % t PLZ Qn OUTPUT LOW - to - OFF OFF - to - LOW t PHZ Q n OUTPUT HIGH - to - OFF OFF - to - HIGH outputs enabled 90 % VM (1)
tf
t PZL VM (1) 10 % t PZH VM (1) outputs disabled outputs enabled
MGA656
(1) HC : HCT :
VM = 50%; VI = GND to VCC. VM = 1.3 V; VI = GND to 3 V.
Fig.17 Waveforms showing the 3-state enable and disable times for input OE.
September 1993
20
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
APPLICATION INFORMATION
74HC/HCT7404
handbook, full pagewidth
OE SI SI D0 D1 D2 D3 D4 DIR MR OE DOR Q0 Q1 SI D0 D1 D2 D3 D4 DIR MR OE DOR Q0 Q1
DOR
7404
Q2 Q3 Q4 SO
7404
Q2 Q3 Q4 SO
10-bit data
10-bit data
SI D0 D1 D2 D3 D4
OE DOR Q0 Q1
SI D0 D1 D2 D3 D4
OE DOR Q0 Q1
7404
Q2 Q3 Q4 SO
7404
Q2 Q3 Q4 SO SO
MGA686
DIR MR DIR MR
DIR MR
Fig.18 Expanded FIFO (parallel and serial) for increased word length; 10 bits wide x 64 n-bits.
September 1993
21
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
DATA INPUT COMPOSITE DIR FLAG SI MR
5
Dn DIR SI MR
Qn DOR
5
DATA OUTPUT COMPOSITE DOR FLAG SO OE
7404
SO OE
DIR SI
DOR SO
7404
MR DATA INPUT 5 Dn OE Qn
MGA681
5
DATA OUTPUT
Fig.19 Expanded FIFO for increased word length; 64 words x 10 bits.
Note to Fig.19 The "7404" is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay on the flags.
September 1993
22
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
5
Dn DIR
Qn DOR
5
Q composite DIR Q Q
D
7404
SI MR SO OE
D
Q
74
CP
74
CP Q
composite DOR
D CP DIR SI MR 5 SI DOR SO SO OE 5
D CP
Q
QR
RQ
7404
MR Dn OE Qn
MGA685
Fig.20 Expanded FIFO for increased word length.
Note to Fig.20 This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are started (see Fig.8 and Fig.10). Expanded format Figure 21 shows two cascaded FIFOs providing a capacity of 128 words x 5 bits. Figure 22 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a ripple through delay, data arrives at the output of FIFOA. Due to SOA being HIGH, a DORA pulse is generated. The requirements of SIB and DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple through delay, data arrives at the output of FIFOB. Figure 23 shows the signals on the nodes of both FIFOs after the application of a SOB pulse, when both FIFOs are initially full. After a bubble-up delay a DIRB pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH. Figure 24 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
September 1993
23
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
DOR A SO A SI DIR SI A DIR A 5 DnA MR MR OE OE
SI B DIR B
DOR B SOB
DOR SO 5 DATA OUTPUT
7404
FIFO A Q nA 5 DnB
7404 Q nB
FIFO B
DATA INPUT
MR
OE
MGA682
Fig.21 Cascading for increased word capacity; 128 word x 5 bits.
Note to Fig.21 The "7404" is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary communications are handled by the FIFOs. Figures 22 and 23 demonstrate the intercommunication timing between FIFOA and FIFOB. Figure 24 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and shifted empty again.
September 1993
24
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
DIR A
VM
(1)
SI A
VM (1)
2
ripple through delay DOR A SI B VM
4
(1)
DIR B SO A 1
5
VM (1)
6
Q nA DnB
3 ripple through delay
DOR B
7
VM (1)
Q nB
MGA666
Fig.22 FIFO to FIFO communication; input timing under empty condition.
Notes to Fig.22 1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data 2. Load one word into FIFOA; SI pulse applied, results in DIR pulse 3. Data-out A/data-in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFOB 4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output ready pulse, data is shifted into FIFOB 5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete 6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation of additional data 7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output stage.
September 1993
25
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
DOR B
VM (1)
SO B
VM
(1)
2
bubble - up delay DIR B SO A
3 VM (1)
DOR A SI B
1
4
VM (1)
5
Q nA DnB bubble - up delay DIR A
6 VM (1)
MGA667
Fig.23 FIFO to FIFO communication; output timing under full condition.
Notes to Fig.23 1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up 2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse 3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is shifted out of FIFOA 4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete 5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting bubble-up of empty location 6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
September 1993
26
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
sequence 1
sequence 2
sequence 3
sequence 4
sequence 5
sequence 6
SO B INPUT (3) DORB OUTPUT (4)
(8)
(14)
Q nB OUTPUT
DIRB OUTPUT
(5) (9)
(13)
DORA OUTPUT
(2)
(6)
(12)
QnA OUTPUT (10) DIRA OUTPUT (7)
SI A INPUT
(1)
(11)
DnA INPUT
MR INPUT
MGA687
Fig.24 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.19).
Note to Fig.24 Sequence 1 (both FIFOS empty, starting SHIFT-IN process) After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes HIGH (4).
September 1993
27
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
Sequence 2 (FIFOB runs full) After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being empty. Sequence 3 (FIFOA runs full) When 65 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. Sequence 4 (both FIFOs full, starting SHIFT-OUT process) SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11).
74HC/HCT7404
Sequence 5 (FIFOA runs empty) At the start of sequence 5 FIFOA contains 63 valid words due to two words being shifted out and one word being shifted in, in sequence 4. An additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted into FIFOB. DORA remains LOW (12). Sequence 6 (FIFOB runs empty) After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses, DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
28

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